Multiphase clock

Multiphase clock

Dec

29

2009

I have found an interesting bug in my design that opened my eyes to one important aspect. The problem is related to the memory chips’ /WE (write enable) signal which should be asserted when I want to store data in memory. With nearly every TTL device in my design being synchronous, altering their states on ...
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Design · Design - control · Design - memory

Microcode pre-release

Nov

29

2009

I decided to stop at this point and declare the initial version of the microcode complete (although the machine has not been simulated yet and the microcode is still untested). I have not yet completed faults and interrupts microcode, because I don’t know how I am going to do user/supervisor mode context switching and which ...
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Design - control

Bitwise shifts – here comes the shifter

Bitwise shifts – here comes the shifter

Nov

27

2009

I have added yet another component to the high level design. It is a shifter and its role is to… shift. More specifically, it is a right shifter which will allow me to perform bitwise right shift in just one clock cycle. Until now, the design was lacking this ability. Doing left shifts is fairly ...
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Design - ALU

Architecture update

Architecture update

Nov

17

2009

At a certain point when microcoding I realized that my architecture was obviously wrong in one aspect. Frankly speaking it was so wrong that I am embarrassed I had not noticed this earlier. The problem was that all address registers were connected to the 8-bit data bus. With such layout, every address loading operation consumed ...
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Design

Block diagram

Block diagram

Nov

1

2009

As I am working through the microcode (and the microcode assembler) this finally required me to sketch a block diagram of the entire machine and the CPUs internal datapaths. The microcode is not ready yet (I have completed about 20 most typical instructions), neither is the assembler (I am adding features to the lexer and parser ...
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Design

Sequencer tweaks

Sequencer tweaks

Oct

19

2009

When I started writing first microcode and sketching the overall block diagram I decided to tweak the microcode sequencer again a little. Here’s what has changed. Fetch. The 9-bit base address points to two 256-element pages. Addresses in page 00h-FFh store instructions directly visible to programmer, whereas page 100h-1FFh is reserved for pseudo-instructions which are ...
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Design - control