BYTEC/16

Schematics

Jun

6

2010

I have successfully come to an end of schematics drawing. It was a challenging task, considering I had zero experience in this matter and the final design is quite complex in terms of number of components and nets. In a hope I didn’t make many mistakes I am publishing the results today and declaring the ...

New instructions, final test run and Fibonacci

May

2

2010

Just a quick summary of what I have been doing over the last few sessions in the project. New instructions Before I continue with hardware I decided to add a few instructions I should have added a long time ago but somehow never got to it. The instructions are shorter versions of some load/store instructions I ...

Memory module 2

Apr

24

2010

I have completed the design of the memory module – the last required module to announce the entire design finished. I chose a very simple design, with rudimentary paging mechanism, in a hope it will not turn out to be a significant limitation in the near future. The machine features a 22-bit physical address bus, ...

Faults and interrupts

Mar

14

2010

It’s been a while since I last posted and in fact I haven’t been working on the project much recently. My job is keeping me extremely busy again. Still, I made some progress on faults and interrupts mechanism for the CPU which I never managed to document. I simulated and tested the design, so it is time to ...

Test suite

Jan

31

2010

A test suite to validate the microcode and my current software toolchain is now complete and has successfully passed. I wrote, assembled and simulated a set of simple test cases for each instruction I have in the instruction set to prove they all work as intended. The suite in total is several hundred lines of ...

Random findings and tweaks from testing

Jan

25

2010

While I am nearing completion of a CPU test suite, there are some findings I would like to share here, as they changed some of my previous assumptions. Besides, they are important aspects for future programming, so I need to remember these. Carry/borrow flag. First thing is how the ‘181 ALU handles the carry flag ...

Schematics

New instructions, final test run and Fibonacci

Memory module 2

Faults and interrupts

Test suite

Random findings and tweaks from testing

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