Microcode Word

The CPU uses a wide microcode word (4-bytes) used to generate control signals (which perform the actual machine instructions). This page documents the microcode word structure and used field values. Fields are listed left to right, starting with most significant bits of microcode bank #0. Field values are encoded big-endian, and are listed in order, e.g. for LBUS the values MDR, A, X, Y correspond to binary codes 00, 01, 10, 11, respectively.

Field Length Bank Values (lowest binary value first)
Default Description
LBUS 2 0 MDR, A, X, Y MDR Left bus drive enable register select
RBUS 3 0 MDR, MSW, ABUS, IPTR, PPC, nc, nc, nc MDR Right bus drive enable register select
ADRBUS 2 0 MAR, SP, DP, PC PC Address bus drive enable register select
BUSIFCMODE

MISC_LATCH

2 0/1 MEM2ALULO, MEM2ALUHI, ALULO2MEM, ALUHI2MEM

LATCH_I, LATCH_S, nc, LATCH_NONE

LATCH_NONE

Bus interface direction and mode (if BUSIFCEN=0)

Latch individual MSW flags (if BUSIFCEN=1)

BUSIFCEN 1 1 enable, disable disable Bus interface enable signal
LOAD 4 1 MDRLO, MDRHI, MDR, ALO, AHI, A, X, Y, MEM, MARLO, MARHI, MAR, SP, DP, PC, MSW MDR Load enable register select
LOAD_IR 1 1 enable, disable disable Load IR register signal
ALUOP 4 1/2 as in 74LS181 function input Y->A (LBUS) ALU function
ALUMODE 1 2 ARITHMETIC, LOGIC ARITHMETIC ALU mode
ALUCARRYIN 1 2 carry, no carry no carry ALU carry input enable signal
ALUSHR 1 2 enable, disable disable ALU right shifter enable signal
LOADFLAGS 2 2 WORD, HI_BYTE, LO_BYTE, disable disable ALU flags latch mode
INCPC 1 3 enable, disable disable PC++ enable signal
INCMAR 1 3 enable, disable ddisable MAR++ enable signal
CNTSP 1 3 enable, disable disable SP count enable signal
CNTSPDIR 1 3 down, up up SP count direction
MEMSEG 1 3 CODE, DATA CODE Memory segment selection
SUPERVISOR 1 3 disable, enable disable Privileged (supervisor) instruction signal (active high)
not connected 2 3 n/a n/a not connected

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