BYTEC/16 rev 2.0 gets MMU

BYTEC/16 rev 2.0 gets MMU
BYTEC is undergoing a hardware revision and will soon receive a set of new features. Recently, while fiddling with monitor/OS and thinking what it would take to implement memory management in Minix, I realized that BYTEC’s memory system is way too simplistic and would lead to serious limitations. So, BYTEC/16 rev 2.0 is on its ...

Memory system update

Memory system update
My memory system has recently undergone an update to hardware design. Originally I planned and implemented four memory bank registers – two for lower and upper 32kB of code, and two for lower and upper 32kB of data (see this post for details). With hardware able to address maximum of 128 banks via 22-bit address ...

Memory module 2

Memory module
I have completed the design of the memory module – the last required module to announce the entire design finished. I chose a very simple design, with rudimentary paging mechanism, in a hope it will not turn out to be a significant limitation in the near future. The machine features a 22-bit physical address bus, ...

Multiphase clock

Multiphase clock
I have found an interesting bug in my design that opened my eyes to one important aspect. The problem is related to the memory chips’ /WE (write enable) signal which should be asserted when I want to store data in memory. With nearly every TTL device in my design being synchronous, altering their states on ...