New instructions, final test run and Fibonacci

Just a quick summary of what I have been doing over the last few sessionsĀ in the project. New instructions Before I continue with hardware I decided to add a few instructions I should have added a long time ago but somehow never got to it. The instructions are shorter versions of some load/store instructions I ...

Gate-level simulator

Gate-level simulator
The simulator is ready and running first simulations of my CPU, proving for the first time that the envisioned mesh of wires and chips may actually work. Writing the simulator was not easy, but I think it was a great exercise. Not using Verilog for this purpose was not a bad idea at all. The ...