Serial ports (based on 16550D UARTs) 5

Serial ports (based on 16550D UARTs)

May

2

2011

With the CPU completed, it is time to think of an I/O to be able to play with the system somewhat more interactively than by plugging EPROM chips in and out and attaching logic probes to data and memory buses. At first, my plan was to build a PS/2 keyboard controller (input) and a rudimentary ...
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Design - I/O

Race conditions 2

Race conditions

Mar

21

2011

I think I am running into all kinds of logic design pitfalls possible. Although it slows me down quite a bit, I consider this an excellent educational experience. Race conditions is what hit me this time. In general a race condition is a state of a logic system in which particular logic gate temporarily outputs ...
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Design - control

Embarrassing flip-flop bug, again 2

Jan

26

2011

I found a nasty design bug yesterday. Some time ago, when I was approaching the end of preliminary hardware verification, having successfully completed tests for most of the instructions, I suddenly bumped into the wall. Problems occurred when I was trying to exercise my faults and interrupts mechanism. It didn’t work at all, causing the system ...
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Construction · Design

Bus-hold

Bus-hold

Dec

29

2010

There is one aspect of logic design I’ve been totally neglecting, at least until now. It is related to unconnected (floating) inputs of certain families of 74-series chips. I realized this having read a couple of articles on the web, particularly this article comparing TTL and CMOS families, this class on allaboutcircuits.com, and this paper from Texas Instruments. I am not an electrical ...
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Construction · Design

Short update on MDR

Short update on MDR

Dec

5

2010

I reviewed the microcode while implementing the MDR workaround I discussed yesterday. I realized that the problem affects currently only 5 instructions, namely: ADD AH, (SP) SUB AH, (SP) CMP AH, (SP) SHL AH SHR AL I took advantage of MDR clearing whenever I manipulated the low or high byte of A register, using the ...
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Design

Silly MDR flaw

Silly MDR flaw

Dec

5

2010

I have come across the first real design flaw in my CPU. By design flaw I mean a real design flaw, with something functioning not exactly as designed, not an accidentally swapped wire or a simple bug in schematics. The good news is that it going to be fairly easy to fix. The bad news ...
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Construction · Design