More bugs

More bugs

Jun

14

2011

Recent exercises with UART revealed two interesting bugs in my design. Both problems were resolved and I am documenting them here for dairy keeping. Implicit memory reads It is something I have discovered only now, playing with real devices attached to the CPU’s expansion bus. The problem is related to side effects of implicitly reading ...
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Design · Design - control

It talks! 5

It talks!

May

28

2011

I now have a computer with support for RS-232 serial communications. Since my last post I managed to build and preliminarily test the new device card with two 16550 UART chips. Somehow it makes me very excited, because for the first time I will be able to communicate with my system by means of keyboard ...
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Construction

UARTs board draft schematics

UARTs board draft schematics

May

7

2011

I completed the initial revision of UARTs board schematics last night. Both 16550 UART chips and MAX232 level converters were new to me, so the task took several hours. Unlike with simple TTL chips, this time I really had to study the datasheets carefully to understand what all those pins do. I am only going ...
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Design - I/O

Serial ports (based on 16550D UARTs) 5

Serial ports (based on 16550D UARTs)

May

2

2011

With the CPU completed, it is time to think of an I/O to be able to play with the system somewhat more interactively than by plugging EPROM chips in and out and attaching logic probes to data and memory buses. At first, my plan was to build a PS/2 keyboard controller (input) and a rudimentary ...
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Design - I/O

Hardware testing completed 3

Hardware testing completed

Mar

27

2011

Yes – the wire wrapped CPU prototype now passes all tests. Since I finished construction a couple of months ago I have been trying to eliminate all outstanding logic bugs and make the machine more stable. Only at this point I am confident enough to declare the preliminary QA phase completed and happily spread this ...
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Construction · General

Race conditions 2

Race conditions

Mar

21

2011

I think I am running into all kinds of logic design pitfalls possible. Although it slows me down quite a bit, I consider this an excellent educational experience. Race conditions is what hit me this time. In general a race condition is a state of a logic system in which particular logic gate temporarily outputs ...
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Design - control