Yes – the wire wrapped CPU prototype now passes all tests. Since I finished construction a couple of months ago I have been trying to eliminate all outstanding logic bugs and make the machine more stable. Only at this point I am confident enough to declare the preliminary QA phase completed and happily spread this good news. On the way I had to rebuild some of the circuitry (the MSW, the MDR, parts of control logic), adjust microcode to match new hardware, fix a few assembler bugs to mention just the most significant changes. Of course, at all times I needed to keep the schematics and simulator code in sync. It was a challenging but very interesting journey. With little time I have had recently, I am happy to have accomplished this.
My plan for the nearest future is to build an I/O subsystem. I will start with a LCD character display, because it should be fairly easy to add (on an expansion card) and will provide a decent debug display to support consequent step which I think will be a simple PS/2 keyboard interface and serial port (based on 16550 UART chips). This will finally make my computer more interactive and allow me to write and run a couple of useful demo programs. At this point I also think my gate-level machine simulator has already fulfilled its role. I will not develop it any longer, instead I will probably think of a functional simulator (or should I say emulator?) to help me test and debug new software for the CPU on a PC.
Today I am releasing all project source codes and schematics. The release is mostly bug fixing (both in hardware and software). The revised schematics is particularly important, as it turned out that the previous version was not fully operational. As usual, all project resources are in downloads.
I am leaving for a 15-day vacation next week. I really need a rest from my paying job, which has been so hectic recently. This project will have a short break too, but I will pick it up again as soon as I return.