Multiphase clock

Multiphase clock
I have found an interesting bug in my design that opened my eyes to one important aspect. The problem is related to the memory chips’ /WE (write enable) signal which should be asserted when I want to store data in memory. With nearly every TTL device in my design being synchronous, altering their states on ...

Microcode pre-release

I decided to stop at this point and declare the initial version of the microcode complete (although the machine has not been simulated yet and the microcode is still untested). I have not yet completed faults and interrupts microcode, because I don’t know how I am going to do user/supervisor mode context switching and which ...

Sequencer tweaks

Sequencer tweaks
When I started writing first microcode and sketching the overall block diagram I decided to tweak the microcode sequencer again a little. Here’s what has changed. Fetch. The 9-bit base address points to two 256-element pages. Addresses in page 00h-FFh store instructions directly visible to programmer, whereas page 100h-1FFh is reserved for pseudo-instructions which are ...

On microcode sequencing again. Final?

On microcode sequencing again. Final?
I’ve changed my mind on microcode sequencing. Again. Ok, I know I would be fired if all this was for real, but I don’t like the sequencer design with ‘next’ field embedded in the microcode word anymore. The problem is with the ‘next’ field itself which I planned to be longer that 8 bits. This requires not ...

More on microcode sequencing

More on microcode sequencing
It’s been a long time since I last posted on this site or did anything related to the project. Way too long. My paying job has had me extremely busy lately. Add to this a long awaited apartment flip we had, sooner than expected due to our contractor’s change of schedules and you’ve got the story. I ...

Thoughts on microcode sequencing 2

Thoughts on microcode sequencing
Back from a 3-week long vacation in Cuba. Time to get back to work. As mentioned before, the machine will be a typical CISC with a wide microcode word, with little encoding. That means that bits from microcode ROM will be directly used as control signals. This is in contrast to a RISC-like approach, where ...