Syncing the clocks

Few months ago I made what I believe was the last hardware fix in the current build. I realized only yesterday that I have not posted the revised schematics, so today’s post is to make up for it.

The fix itself is a simple but important update to the clock generation circuit. In my post from January last year I explained how I implemented CPU wait states to enable I/O with slow external devices. The design uses two pairs of flip flops wired to form two Johnson counters. One Johnson counter generates master clock signals with 90-degree phase offset (CLK0 and CLK1). Whenever a special /IO signal becomes low active (indicating that the CPU executes I/O with device mapped in a memory range $1000h-$1FFFh) a one-clock-long delay is inserted in the second (low) half of the master clock. This is a wait state, and the system stalls for a while to give a device enough time to finish its job. How does the CPU leave the wait state? This is when the second Johnson counter comes in – it generates an auxiliary clock signal which is only used for wait state timing and to trigger the master clock out of it.

For the above to work, both master clock and the auxiliary clock need to be in sync. I silently hoped that this could be achieved out-of-the-box by simply powering-up 74LS74 chips at the same time. Not really. One should not make any assumptions about the logic state in which a TTL chip powers-up. It is not mentioned anywhere in the datasheet, so the initial logic state is random, even for chips from the same manufacturer. The consequence of this bug was that my master and auxiliary clocks could be opposite phase with back luck on power-up. The CPU sometimes worked, and sometimes not.

My first idea to fix it was to use a /RESET signal on the flip-flop’s /CLR or /PRE inputs. This however, would keep the output of the clock flip-flop low or high, respectively, until /RESET low active period has finished. Effectively, there would be no system clock during /RESET which is undesirable, as most of my synchronous chips would not be set-up correctly. Even /RESET generation itself requires a clock to strobe the MAX1232 reset generator, otherwise the system would never launch.

So I needed an additional reset signal which would be shorter than system-wide /RESET and would activate the Johnson counters’ reset inputs, thus synchronizing them on power up. I used a simple RC circuit and a schmitt trigger (in reality two inverting schmitt triggers) to generate such pre-reset. I used a 10kΩ resistor and 10uF capacitor. This results in a 50ms low signal used to reset the flip-flop pairs. Here is a before and after schematics extract (note the RC circuit in the lower left corner):

clocks before

Clocks without the syncing circuit

clocks sync

Clocks with RC syncing circuit

With this change, the CPU powers-up with no problems at all times. The complete updated schematics has been posted to downloads page.

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