I have added yet another component to the high level design. It is a shifter and its role is to… shift. More specifically, it is a right shifter which will allow me to perform bitwise right shift in just one clock cycle. Until now, the design was lacking this ability. Doing left shifts is fairly easy and can be computed in one cycle without any shifter, simply by adding a number to itself. Unfortunately, performing right shifts using this scheme for 16-bit numbers would require 15 left shifts (15 additions), analyzing the carry flag in each step and adding its value to the least significant bit. With the shifter in place, there is no such asymmetry between SHL and SHR operations.
In hardware terms the shifter will be built using two 74LS244 drivers, one wired like a regular buffer and the other wired so that it does a bitwise right shift (most significant bit is hardwired zero or a current carry flag, least significant bit becomes a new carry flag). There is also a dedicated microcode bit and corresponding control line to choose between the two.
It looks nice but there is a significant drawback to this approach. Additional component between the ALU and the ALUBUS complicates flags generation circuitry even more. Currently I have mostly 16-bit instructions, and for some of them their 8-bit counterparts for higher or lower byte of registers, which already complicates things. To correctly determine the flags (C, Z, N, V) I now need to take into account what the ALU outputs, and:
- whether I am performing a 16-bit op or an 8-bit op
- for 8-bit ops, whether it is a high byte or a low byte op
- whether the shifter is active or not
This accounts for six distinct combinations, some extra wires and multiplexing, but I will go for it.